As integrated memory circuits are scaled down to increase capacity it becomes desirable to reduce the power supply voltage. However, the memory cells (e.g., static random access memory or SRAM cells) and sense amplifiers (SA's) are very sensitive to reductions in the applied voltage. As the voltage is reduced, there is an increase in memory write and read errors due, for example, to ambiguity in the value of a charge stored by the memory cell, e.g., soft errors. To reduce power consumption and enable further reduction in circuit size, one approach is to reduce a voltage level supplied to circuits other than the memory cell array (e.g., decoders, clock circuits) while maintaining the voltage supplied to the memory cells at some desirable level. Even though the memory cells continue to be operated at the higher voltage and power levels, the net effect is to substantially reduce power consumption because the support circuits are continually operating while only a small number of the memory cells (e.g., only those actually being accessed) are fully powered at any particular time.
Implementing a sufficiently high voltage differential within a memory cell array while using a reduced voltage for other memory structures and interfacing devices may be accomplished by the use of level shifters to interface the components. For example, a “high” voltage differential with a low logic level of 0 V and a high logic level of 1.3 V may be used within a memory cell array while a high logic level of only 0.7 V may be used outside the array for other memory structures (e.g., support circuitry for/associated with the memory cell array such as address decoders and timing circuits) and interfacing devices (e.g., address and data busses.) A transition from the low to the higher voltage logic levels may be accomplished using level shifters. Level shifters convert the low voltage logic levels to the higher voltages required by the memory cells of a memory cell array. While reducing power requirements, incorporating these level shifters consumes additional energy to power the level shifters and requires additional area or space on a chip (e.g., chip substrate “real estate”.) The level shifters may also introduce a delay in signal propagation time, skewing clock, control and data signals. Thus, the number and configuration of level shifters can affect memory size, timing and power requirements.